Product Summary

The SST27SF512-70-3C-PGE is a 64K 128K CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The MTP SST27SF512-70-3C-PGE can be electrically erased and programmed at least 1000 times using an external programmer with a 12V power supply. They have to be erased prior to programming. The SST27SF512-70-3C-PGE conform to JEDEC standard pinouts for byte-wide memories. Featuring high-performance Byte-Program, the SST27SF512-70-3C-PGE provide a Byte-Program time of 20 μs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years.

Parametrics

SST27SF512-70-3C-PGE absolute maximum ratings: (1)Temperature Under Bias: -55 to +125℃; (2)Storage Temperature: -65 to +150℃; (3)D. C. Voltage on Any Pin to Ground Potential: -0.5V to VDD+0.5V; (4)Transient Voltage (<20 ns) on Any Pin to Ground Potential: -2.0V to VDD+2.0V; (5)Voltage on A9 and VPP Pin to Ground Potential: -0.5V to 14.0V; (6)Package Power Dissipation Capability (TA = 25): 1.0W; (7)Through Hole Lead Soldering Temperature (10 Seconds): 300℃; (8)Surface Mount Solder Reflow Temperature: 260℃ for 10 seconds; (9)Output Short Circuit Current: 100 mA.

Features

SST27SF512-70-3C-PGE features: (1)4.5-5.5V Read Operation; (2)Superior Reliability; (3)Low Power Consumption; (4)Fast Read Access Time; (5)Fast Byte-Program Operation; (6)Electrical Erase Using Programmer; (7)TTL I/O Compatibility; (8)JEDEC Standard Byte-wide EPROM Pinouts; (9)Packages Available; (10)All non-Pb (lead-free) devices are RoHS compliant.

Diagrams

SST27SF512-70-3C-PGE functional block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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SST27SF512-70-3C-PGE
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Data Sheet

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